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SH69P25
PRELIMINARY
Features
SH6610C-based single-chip 4-bit micro-controller OTPROM: 4096 X 16 bits RAM: 160 X 4 bits (data memory) Operation voltage: 2.4V - 6.0V (typical 3.0V or 5.0V) 22 CMOS bi-directional I/O pins Built in pull-up and pull-low resistor for PortA ~ PortF 4-level subroutine nesting (including interrupts) One 8-bit auto re-load timer/counter Warm-up timer for power on reset Powerful interrupt sources: - Internal interrupt (Timer0) - External interrupts: PortB & PortC (rising/falling edge) Oscillator (OTP option) - Xtal oscillator: 32.768kHz - 4MHz - Ceramic resonator: 400k - 4MHz - RC oscillator:400k - 4MHz - External clock: 30k - 4MHz Instruction cycle time: - 4/32.768kHz(122us) for 32.768kHz OSC clock - 4/4MHz (1us) for 4MHz OSC clock Two low power operation modes: HALT and STOP Built-in watch dog timer (OTP option) Built-in power on reset Two LPD level(OTP option) - High level: 4.0V - Low level: 2.5V OTP type &Code protection
OTP 4-bit Microcontroller
General Description
SH69P25 is a 4-bit micro controller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 4K OTPROM, Timer and I/O Ports.
Pin Configuration
PE2 PE3 PF1 PA2 PA3 T0 RESET GND PB0 PB1 PB2 PB3 PD0 PD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PE1 PE0 PF0 PA1 PA0 OSCI OSCO VDD PC3 PC2 PC1 PC0 PD3 PD2
SH69P25
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V1.01
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SH69P25
Block Diagram
RESET OSCO OSCI
OSC WDTEN RC RESET WATCHDOG TIMER PRESCLALER
CPU
PORTA ( 4-BITS ) PORTA [0:3] PORTB ( 4-BITS )
Power on
PORTB [0:3] LPD CTL REG. LPDON T0 8-BITS TIMER ( Up counter ) OTPROM 4096*16 BITS PORTE ( 4-BITS ) TIMER INTERRUPT DATA RAM 160*4 BITS PORTF ( 2-BITS ) PORTF [0:1] PORTE [0:3] PORTD (4-BITS ) PORTD [0:3] PORTC [0:3] PORTC ( 4-BITS )
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Pin Description(Normal mode)
Pin No. 27, 28, 1, 2 26, 3 24, 25, 4, 5 6 7 8 9 - 12 13- 16 17 - 20 21 22 23 Designation PE[0:3] PF[0:1] PA[0:3] T0 RESET GND PB[0:3] PD[0:3] PC[0:3] VDD OSCO OSCI I/O I/O I/O I/O I I P I/O I/O I/O P O I Bit programmable I/O Bit programmable I/O Bit programmable I/O. Timer Clock/Counter input pin. (Schmitt trigger input) Reset input (active low, Schmitt trigger input). Ground pin Bit programmable I/O. Vector Interrupt (Active rising or falling edge by system register setup) Bit programmable I/O Bit programmable I/O. Vector Interrupt (Active rising or falling edge by system register setup) Power supply pin OSC output pin. No output in RC mode OSC input pin, connected to a crystal, ceramic or external resistor. Descriptions
OTP Programming Pin Description (OTP program mode)
Pin No. 21 7 8 23 24 Symbol VDD VPP GND SCK SDA I/O P P P I I/O Shared by VDD RESET GND OSCI PA[0] Description Programming Power supply (+5.5V) Programming high voltage Power supply (+10.5V) Ground Programming Clock input pin Programming Data pin
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Function Description
1. CPU The CPU contains the following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, and DPL), and the Stack. 1.1. PC (Program Counter) The Program Counter is used to address the 4K program ROM. It consists of 12-bits: the Page Register (PC11), and the Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). The program counter normally increases by one (+1) with every execution of an instruction except in the following cases: (1) When executing a jump instruction (such as JMP, BA0, BAC), (2) When executing a subroutine call instruction (CALL), (3) When an interrupt occurs, (4) When the chip is in the INITIAL RESET mode. The program counter is loaded with data corresponding to each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. 1.2. ALU and CY ALU performs arithmetic and logic operations. The ALU provides the following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment for addition/subtraction (DAA, DAS) Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) Decision (BA0, BA1, BA2, BA3, BAZ, BAC) Logic Shift (SHR) The Carry Flag (CY) holds the ALU overflow which the arithmetic operation generates. During an interrupt servicing or call instruction, the carry flag is pushed into the stack and retrieved back from the stack by the RTNI instruction. It is unaffected by the RTNW instruction. 1.3. Accumulator The Accumulator is a 4-bit register holding the results of the arithmetic logic unit. In conjunction with the ALU, data transfer between the accumulator and system register or data memory can be performed. 1.4. Stack A group of registers are used to save the contents of CY & PC (10-0) sequentially with each subroutine call or interrupt. It is organized into 13 bits X 4 levels. The MSB is saved for CY. 4 levels are the maximum allowed for subroutine calls and interrupts. The contents of the Stack are returned sequentially to the PC with the return instructions (RTNI/RTNW). The stack is operated on a first-in, last-out basis. This 4-level nesting includes both subroutine calls and interrupts requests. Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4, and the bottom of the stack will be shifted out.
2. OTPROM The SH69P25 can address up to 4096 X 16 bit words of program area from $000 to $FFF. Service routine as starting vector address. Address $000H $001H $002H $003H $004H Instruction JMP Instruction NOP JMP Instruction NOP JMP Instruction Remarks Jump to RESET service routine Reserved Jump to TIMER0 service routine Reserved Jump to PBC service routine
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3. RAM The built-in RAM consists of general-purpose data memory and the system register. Direct addressing in one instruction can access both data memory and the system register. The following is the memory allocation map: $000 - $01F: System register and I/O. $020 - $0BF: Data memory (160 X 4 bits, divided into 2 banks. $020 - $07F: bank0, $080 - $0BF: bank1). (a) The Configuration of the System Register Address $00 $01 $02 $03 $04 $05 $06-$07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 - $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F PULLEN Bit3 TL0.3 TH0.3 PA.3 PB.3 PC.3 PD.3 PE.3 TBR.3 INX.3 DPL.3 Bit2 IET0 IRQT0 TM0.2 TL0.2 TH0.2 PA.2 PB.2 PC.2 PD.2 PE.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 Bit1 TM0.1 TL0.1 TH0.1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 Bit0 IEP IRQP TM0.0 TL0.0 TH0.0 PA.0 PB.0 PC.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt enable flags Interrupt request flags Timer0 Mode register (Prescaler) Reserved Timer0 load/counter register low digit Timer0 load/counter register high digit Reserved PORTA PORTB PORTC PORTD PORTE PORTF Table Branch Register Pseudo index register Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble Reserved Bit1:PBC interrupt rising / failing edge set Bit2:Port pull-hi/low set Bit3: Port pull-up/low enable control PA3OUT PA2OUT PA1OUT PA0OUT PB3OUT PB2OUT PB1OUT PB0OUT PC3OUT PC2OUT PC1OUT PC0OUT PD3OUT PD2OUT PD1OUT PD0OUT PE3OUT PE2OUT PE1OUT PE0OUT WDT PF1OUT T0S PF0OUT T0E R/W R/W R/W R/W R/W R/W R/W W Set PORTA as an output port Set PORTB as an output port Set PORTC as an output port Set PORTD as an output port Set PORTE as an output port Set PORTF as an output port Bit0: T0 signal edge; Bit1: T0 signal source Reserved Bit3: WDT timer reset (write 1 to reset WDT) Reserved Remarks
PH/PL
PBCFR
-
R/W
* System Register $00 - $12 (except $07H) refer to "SH6610C User manual".
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(b) System Register state: Bit 3 $00 $01 $02 $03 $04 $05 $06-$07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 - $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F PULLEN PA3OUT PB3OUT PC3OUT PD3OUT PE3OUT WDT PH/PL PA2OUT PB2OUT PC2OUT PD2OUT PE2OUT PBCFR PA1OUT PB1OUT PC1OUT PD1OUT PE1OUT PF1OUT T0S PA0OUT PB0OUT PC0OUT PD0OUT PE0OUT PF0OUT T0E TL0.3 TH0.3 PA.3 PB.3 PC.3 PD.3 PE.3 TBR.3 INX.3 DPL.3 Bit 2 IET0 IRQT0 TM0.2 TL0.2 TH0.2 PA.2 PB.2 PC.2 PD.2 PE.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 Bit 1 TM0.1 TL0.1 TH0.1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 Bit 0 IEP IRQP TM0.0 TL0.0 TH0.0 PA.0 PB.0 PC.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 Power On Reset /Pin Reset / Low Voltage Reset -0-0 -0-0 - 000 0000 0000 1111 1111 1111 1111 1111 - -11 xxxx xxxx xxxx -xxx -xxx 010 0000 0000 0000 0000 0000 - - 00 - - 00 WDT Reset -0-0 -0-0 - 000 0000 0000 1111 1111 1111 1111 1111 - -11 uuuu uuuu uuuu -uuu -uuu 010 0000 0000 0000 0000 0000 - - 00 - - 00 -
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
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(c) Others initial state: Others Program Counter (PC) CY Accumulator (AC) Data Memory After any Reset $000 Undefined Undefined Undefined
4. Low Power Detection (LPD) The LPD function is used to monitor the supply voltage and applies an internal reset in the micro-controller at the time of battery replacement. If the applied circuit satisfies the following conditions, the LPD can be incorporated using software control. - Power supply voltage VDD = 2.4 to 6.0 V 4.1 Functions of the LPD Circuit The LPD function is selected by OTP option. The LPD circuit has the following functions: - It generates an internal reset signal when VDD VLPD and t tLPD - It cancels the internal reset signal when VDD > VLPD or VDD VLPD and t < tLPD Here, VDD: power supply voltage, VLPD: LPD detect voltage, There are two level selected by OTP option: Low level: 2.3~2.7V, typical 2.5V High level: 3.8~4.2V, typical 4.0V tLPD: 100g s~500g s, typical 300g s LPD can be enabled or disabled permanently by OTP option.
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5. I/O Ports The SH69P25 provides 22 I/O pins. When every I/O is used as an input port, the port control register controls ON/OFF of the output buffer. Sections below show the circuit configuration of I/O ports. Every I/O pin has a internal pull up / pull low resister, which is controled by PULLEN and PH/PL of $15 Each of these ports contains 4 or 2(PF) bits I/O pins. ON/OFF of the output buffer for port can be controlled by the port control register. Port I/O mapping address is shown as follows: Address $08 $09 $0A $0B $0C $0D Bit3 PA.3 PB.3 PC.3 PD.3 PE.3 Bit2 PA.2 PB.2 PC.2 PD.2 PE.2 Bit1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 Bit0 PA.0 PB.0 PC.0 PD.0 PE.0 PF.0 R/W R/W R/W R/W R/W R/W R/W PORTA PORTB PORTC PORTD PORTE PORTF Remarks Power On 1111 1111 1111 1111 1111 - -11
Equivalent Circuit for a Single I/O Pin
VDD PULL EN PH/PL AND AND VDD DATA WRITE RESET DATA IN READ CONTROL WRITE RESET PULL EN PH/PL AND AND GND D PXXOUT CK RESET QB Q OR GND D DATA CK SET QB I/O PIN Q
AND
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System Register $16 - $1B Address $15 $16 $17 $18 $19 $1A $1B Bit3 PULLEN PA3OUT PB3OUT PC3OUT PD3OUT PE3OUT Bit2 PH/PL PA2OUT PB2OUT PC2OUT PD2OUT PE2OUT Bit1 PBCFR PA1OUT PB1OUT PC1OUT PD1OUT PE1OUT PF1OUT Bit0 PA0OUT PB0OUT PC0OUT PD0OUT PE0OUT PF0OUT R/W RW W W W W W W Remarks Bit1:PBC interrupt rising / failing edge set Bit2:Port pull-hi/low set Bit3: Port pull-up/low enable control Set PORTA as an output port Set PORTB as an output port Set PORTC as an output port Set PORTD as an output port Set PORTE as an output port Set PORTF as an output port Power On 010 0000 0000 0000 0000 0000 - - 00
PAXOUT, PBXOUT, PCXOUT, PDXOUT, PEXOUT (X = 0, 1, 2, 3), PFXOUT (X = 0, 1) 1: Use as an output buffer 0: Use as an input buffer (Power on initial) PBCFR: 1: Rising Edge interrupt 0: Falling Edge interrupt, PH/PL: 1: Port Pull up resister ON, 0: Port Pull low resister ON, PULLEN: 1: Port Pull up /Pull low enable, 0: Port Pull up /Pull low disable
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PORTB & PORTC interrupt The PORTB and PORTC are used as port interrupt sources. Since PORT I/O is bit programmable I/O, so only the input port can generate an external interrupt. When PBCFR set to 0, any one of the PORTB and PORTC input pin transitions from VDD to GND will generate an interrupt request. And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD. When PBCFR set to 1, any one of the PORTB and PORTC input pin transitions from GND to VDD will generate an interrupt request. And further rising edge transition would not be able to make interrupt request until all of the pins return to GND. Following is the port interrupt function block-diagram.
PBOUT[3] PB[3] PBOUT[2] PB[2] PBOUT[1] PB[1] PBOUT[0] PB[0] PCOUT[3] PC[3] PCOUT[2] PC[2] PCOUT[1] PC[1] PCOUT[0] PC[0] PBCFR PBOUT[3] PB[3] PBOUT[2] PB[2] PBOUT[1] PB[1] PBOUT[0] PB[0] PCOUT[3] PC[3] PCOUT[2] PC[2] PCOUT[1] PC[1] PCOUT[0] PC[0] PORT INTERRUPT DETECT PORTINT
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6. T0 & WDT System Register $1C Address $1C BIT3 BIT2 BIT1 T0S BIT0 T0E R/W W Remark Bit0: T0 signal edge Bit1: T0 signal source
T0E: T0 signal edge 0: Increment on low-to-high transition T0 pin (Power on initial) 1: Increment on high-to-low transition T0 pin T0S: T0 signal source. 0: OSC 1/4 (Power on initial). 1: Transition on T0 pin.
T0S OSC/4 0 M U X TIMER0 (8bits)
T0 TOE EOR
1
3 Built-in RC Oscillator TM0 [2:0] WDT Enable (OTP option ) WDT reset
WDT & Warm Up Counter
3
WDT Timeout
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System Register $1E Address $1E Bit3 WDT Bit2 Bit1 Bit0 R/W W Remark Bit3: Watchdog timer reset. (write 1 to reset WDT)
The input clock of the watchdog timer is generated by a built-in RC oscillator so that the WDT will always run even in the STOP mode. SH69P25 generates a RESET condition when the watchdog times-out. The watchdog can be enabled or disabled permanently by using the OTP option. To prevent it timing out and generating a device RESET condition, you should write this bit as "1" before timing-out. The WDT has a time-out period of more than 7ms(typical 18ms) . If longer time-out periods are desired, a prescaler with a division ratio of up to 1:2048 can be assigned to the WDT under software controll by writing to the TM0 register. Pre-scaler divide ratio: TM0.2 1 1 1 1 0 0 0 0 TM0.1 1 1 0 0 1 1 0 0 TM0.0 1 0 1 0 1 0 1 0 Prescaler Divide Ratio 1:1 1:2 1:4 1:8 1:32 1:128 1:512 1:2048 (Power on initial) Timer-out Period 7ms(min) 14ms(min) 28ms(min) 56ms(min) 224ms(min) 896ms(min) 3,584ms(min) 14,336ms(min)
0.875ms (min) RC OSC
Internal
SCALER_1
/8
WDT Time out Period 7ms(min) /1 /2
WDT PRESCALER TM0
/4
/8
/32 /128
/512
/2048
Final WDT Time out period
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7. Timer0 SH69P25 has one 8-bit timer. The time/counter has the following features: . 8-bit timer/counter . Readable and writeable . Automatic reloadable counter . 8-prescaler scale is available . Internal and external clock select . Interrupt on overflow from $FF to $00 . Edge select for external event Following is a simplified timer block diagram:
Fosc/4 PRE-SCALER T0 T0M T0C 8-BIT COUNTER
T0E
T0S
7.1. Configuration and Operation Timer0 consists of an 8-bit write-only timer load register (TL0L, TL0H), and an 8-bit read-only timer counter (TC0L, TC0H). The counter and load register both have low order digits and high order digits. Writing data into the timer load register (TL0L, TL0H) can initialize the timer counter. Load register programming: Write the low-order digit first and then the high-order digit. The timer counter is loaded with the contents of the load register automatically when the high order digit is written or the counter counts overflow from $FF to $00. Timer Load Register: Since the register H controls the physical READ and WRITE operation, please follow these rules: Write Operation: First write Low nibble, Then write High nibble to update the counter.
Read Operation: High nibble first; Followed by Low nibble.
Load Reg. L
Load Reg. H
8-bit timer counter Latch Reg. L
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7.2. Timer0 Interrupt The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt enable flag is enabled, then a timer interrupt service routine will proceed. This can also be used to waken the CPU from HALT mode. 7.3. Timer0 Mode Register The timer can be programmed in several different prescaler ratios by setting the Timer Mode register (TM0). The 8-bit counter counts prescaler overflow output pulses. The timer mode registers (TM0) are 3-bit registers used for timer control as shown in table1. These mode registers select the input pulse sources into the timer. Table 1. Timer 0 Mode Register ($02) TM0.2 0 0 0 0 1 1 1 1 TM0.1 0 0 1 1 0 0 1 1 TM0.0 0 1 0 1 0 1 0 1 Prescaler Divide Ratio /2
11 9 7 5 3 2 1 0
Ratio N 2048 (initial) 512 128 32 8 4 2 1
/2 /2 /2 /2 /2 /2 /2
7.4. External Clock/Event T0 as Timer0 Source When an external clock/event input is used for the TM0, it is synchronized with the CPU system clock. Therefor the external source must follow certain constraints. The output from the T0M multiplex is T0C. It is sampled by the system clock in instruction frame cycle. Therefore it is necessary for the T0C to be high (at least 2 tOSC) and low (at least 2 tOSC). When the prescaler ratio 0 selects /2 , the T0C is the same as the system clock input. Therefore the requirement is as follows T0H = T0CH = T0 high time 2 tOSC + T T0L = T0CL = T0 low time 2 tOSC + T Note: T = 40ns When another prescaler ratio is selected, the TM0 is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical. Then: T0C high time = T0C low time = Where T0 = Timer0 input period N = prescaler value The requirement is, therefore:
4 * t OSC + 2 T N * T0 2 tOSC + T , or T0 N 2
N * T0 2
The limitation is applied for the T0 period time only. The pulse width is not limited by this equation. It is summarized as follows: T0 = Timer0 period
4 * t OSC + 2T N
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8. System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock to the CPU and any peripherals. Instruction cycle time (1) 4/32.768kHz (122us) for 32.768kHz system clock (2) 4/4MHz (1us) for 4MHz system clock 8.1 Oscillator type (1) Crystal oscillator: 32.768KHz - 4MHz.
OSCI C1
Crystal 32.768k - 4MHz OSCO C2
(2) Ceramic resonator: 400kHz - 4MHz.
C1 OSCI Ceramic 400k - 4MHz
OSCO C2
(3) RC oscillator: 400kHz - 4MHz.
VDD R OSCI
C1 = 1000p
OSCO
(4) External input clock: 30KHz - 4MHz.
OSCI
External clock source
OSCO
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9. OTP option (a). Oscillator range 0: OSC @ 32K~2MHz (default) 1: OSC @ 2M ~ 4MHz (b). LPD voltage range 0: High LPD voltage (default) 1: Low LPD Voltage (c): LPD on/off control 0: LPD off (default) 1: LPD on (d): WDT on/off control 0: WDT on (default) 1: WDT off (e): Oscillator select: 000: External clock (default) 100: RC Oscillator 400k~4M 110: Crystal /Ceramic Resonator 400k~4M 111: X'tal 32768Hz 10. In System Programming Notice for OTP For COB(chip on Board) assembling mode, the In System Programming technology is valid for OTP chip of SinoWealth Co.. The Programming Interface of OTP chip must be left on user's application PCB, and users can assemble all components including OTP chip in application PCB before programming OTP chip first. Of course it is accessible that bonding OTP chip only first, then programming code, and assembling the others components at last. Because the programming timing of Programming Interface is very sensitive, so four jumpers are needed (VDD, VPP, SDA, SCK) to separate programming pins from application circuit just as following diagram.
Application PCB SH6XPXX VPP VDD SCK SDA GND OTP Writer VDD
To Application Circuit Jumper
The recommended step is as following for these jumpers: 1) The jumper is Open to separate programming pins from application circuit before programming code. 2) Connect the programming interface with OTP Writer and Begin Programming code. 3) Disconnect OTP writer and short these jumpers when programming is finished. For more detail information please refer to the OTP writer user manual.
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Instruction Set All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. Arithmetic and Logical Instruction Accumulator Type Mnemonic ADC ADCM ADD ADDM SBC SBCM SUB SUBM EOR EORM OR ORM AND ANDM SHR Immediate Type Mnemonic ADI ADIM SBI SBIM EORIM ORIM ANDIM X, I X, I X, I X, I X, I X, I X, I Instruction Code 01000 iiii xxx xxxx 01001 iiii xxx xxxx 01010 iiii xxx xxxx 01011 iiii xxx xxxx 01100 iiii xxx xxxx 01101 iiii xxx xxxx 01110 iiii xxx xxxx AC Function Mx + I Flag Change CY CY CY CY X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) Instruction Code 00000 0bbb xxx xxxx 00000 1bbb xxx xxxx 00001 0bbb xxx xxxx 00001 1bbb xxx xxxx 00010 0bbb xxx xxxx 00010 1bbb xxx xxxx 00011 0bbb xxx xxxx 00011 1bbb xxx xxxx 00100 0bbb xxx xxxx 00100 1bbb xxx xxxx 00101 0bbb xxx xxxx 00101 1bbb xxx xxxx 00110 0bbb xxx xxxx 00110 1bbb xxx xxxx 11110 0000 000 0000 AC Function Mx + AC + CY Flag Change CY CY CY CY CY CY CY CY
AC, Mx Mx + AC + CY AC Mx + AC
AC, Mx Mx + AC AC Mx + -AC + CY
AC, Mx Mx + -AC + CY AC Mx + -AC + 1
AC, Mx Mx + -AC + 1 AC Mx AC
AC, Mx Mx AC AC Mx | AC
AC, Mx Mx | AC AC Mx & AC
AC, Mx Mx & AC 0 AC[3]; AC[0] CY; AC shift right one bit CY
AC, Mx Mx + I AC Mx + -I +1
AC, Mx Mx + -I + 1 AC, Mx Mx I AC, Mx Mx | I AC, Mx Mx & I
Decimal Adjustment Mnemonic DAA X DAS X Instruction Code 11001 0110 xxx xxxx 11001 1010 xxx xxxx Function AC; Mx Decimal adjustment for add. AC; Mx Decimal adjustment for sub. Flag Change CY CY
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Transfer Instructions Mnemonic LDA STA LDI X (, B) X (, B) X, I Instruction Code 00111 0bbb xxx xxxx 00111 1bbb xxx xxxx 01111 iiii xxx xxxx AC Mx Mx AC Function Flag Change
AC, Mx I
Control Instructions Mnemonic BAZ X BNZ X BC X BNC X BA0 X BA1 X BA2 X BA3 X CALL X Instruction Code 10010 xxxx xxx xxxx 10000 xxxx xxx xxxx 10011 xxxx xxx xxxx 10001 xxxx xxx xxxx 10100 xxxx xxx xxxx 10101 xxxx xxx xxxx 10110 xxxx xxx xxxx 10111 xxxx xxx xxxx 11000 xxxx xxx xxxx PC PC PC PC PC PC PC PC ST PC PC AC Function X if AC = 0 X if AC 0 X if CY = 1 X if CY 1 X if AC(0) = 1 X if AC(1) = 1 X if AC(2) = 1 X if AC(3) = 1 CY; PC + 1 X (Not including p) ST; TBR hhhh; llll CY Flag Change
RTNW H, L RTNI HALT STOP JMP X TJMP NOP Where, PC AC -AC CY Mx p ST
11010 000h hhh llll 11010 1000 000 0000 11011 0000 000 0000 11011 1000 000 0000 1110p xxxx xxx xxxx 11110 1111 111 1111 11111 1111 111 1111
CY; PC ST
PC PC
X (Including p) (PC11-PC8) (TBR) (AC)
No Operation
Program counter Accumulator Complement of accumulator Carry flag Data memory ROM page Stack
I | & bbb B TBR
Immediate data Logical exclusive OR Logical OR Logical AND RAM bank RAM bank. Every $7F as one RAM bank. Table Branch Register
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Absolute Maximum Rating*
DC Supply Voltage . . . . . . . . . . . . . . -0.3V to + 7.0V Input Voltage . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Ambient Temperature . . . -40J to + 85J Storage Temperature . . . . . . . . . . .-55J to + 125J
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25J , FOSC = 4MHz, unless otherwise specified) Parameter Operating Voltage Operating Current Stand by Current (HALT) Stand by Current (STOP) Input Low Voltage Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Pull-up/ Pull-low Resistor Output High Voltage Output Low Voltage Symbol VDD IOP ISB1 ISB2 VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 IIL1 IIL2 IIL3 IIL4 IIL5 RP VOH VOL VDD - 0.7 GND + 0.6 -3 -3 GND GND GND 0.8 X VDD 0.85 X VDD 0.85 X VDD -1 -5 1 1 1 150 5 3 3 Min. 4.5 Typ. 5.0 0.6 Max. 6.0 1.0 0.5 1 0.2 X VDD 0.15 X VDD 0.15 X VDD VDD VDD VDD 1 Unit V mA mA A V V V V V V A A A A A K V V All output pins unloaded (Execute NOP instruction) All output pins unloaded Condition
All output pins unloaded,
LPD off (If LPD on, ISB2X = ISB2 + 2A) WDT off (If WDT on, ISB2X = ISB2 + 15A) I/O ports, pins tri-state
RESET , T0
OSCI (Driven by external clock) I/O ports, pins tri-state
RESET , T0
OSCI (Driven by external Clock) I/O ports, GND < VI/O < VDD V RESET = GND + 0.25V V RESET = VDD T0, GND < Vt0 < VDD For OSCI PULL-UP/ PULL-LOW resistor I/O ports, IOH = -10mA I/O ports, IOL = 20mA
AC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25J , unless otherwise specified) Parameter Oscillator Start Time RESET pulse width (low) WDT Period Frequency Stability (RC) Symbol TOSC1 TRESET TWDT F/F 10 7 18 20 Min. Typ. Max. 1 Unit s s ms % VDD = 5.0V VDD = 5.0V RC Oscillator: [F(5.0)-F(4.5)]/F(5.0) Condition X'tal osc = 32.768KHz
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DC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25J , FOSC = 4MHz, unless otherwise specified) Parameter Operating Voltage Operating Current Stand by Current (HALT) Stand by Current (STOP) Input Low Voltage Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Symbol VDD IOP ISB1 ISB2 VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 IIL1 IIL2 IIL3 IIL4 IIL5 VOH VOL -3 -3 VDD - 0.7 GND + 0.4 GND GND GND 0.8 X VDD 0.85 X VDD 0.85 X VDD -1 -5 1 1 1 5 3 3 Min. 2.4 Typ . 3.0 0.3 Max. 4.5 0.6 0.2 1 0.2 X VDD 0.15 X VDD 0.15 X VDD VDD VDD VDD 1 Unit V mA mA A V V V V V V A A A A A V V All output pins unloaded (Execute NOP instruction) All output pins unloaded Condition
All output pins unloaded,
LPD off (If LPD on, ISB2X = ISB2 + 2A) WDT off (If WDT on, ISB2X = ISB2 + 5A) I/O ports, pins tri-state RESET , T0 OSCI (Driven by external clock) I/O ports, pins tri-state RESET , T0 OSCI (Driven by external Clock) I/O ports, GND < Vi/o < VDD V RESET = GND + 0.25V V RESET = VDD T0, GND < Vt0 < VDD For OSCI I/O ports, IOH = -7mA, VDD = 3V I/O ports, IOL = 8mA, VDD = 3V
User Notice: Max. Current into VDD = 100mA; Max. Current out of VSS = 150mA Max. Output current sunk by any I/O port = 50mA; Max. Output current sourced by any I/O port = 40mA
AC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25J Parameter Oscillator Start Time RESET pulse width (low) WDT Period Frequency Stability (RC) Symbol TOSC1 TRESET TWDT F/F 12 7 18 20 Min. Typ . Max. 1
, unless otherwise specified) Unit s s ms % Condition Crystal Osc = 32.768KHz, VDD = 3.0V VDD = 3.0V VDD = 3.0V RC oscillator (1MHz): [F(3.0)-F(2.7)]/F(3.0)
Low Power Detect Electrical Characteristics (a) VDD = 2.4~6V, GND = 0V, TA = 25C, FOSC = 4MHz, unless otherwise specified. Parameter LPD Voltage(Low) LPD Voltage(High) Low power detect ignore time Symbol VLPD1 VLPD2 tLPD Min. 2.3 3.8 100 Typ . 2.5 4.0 300 Max. 2.7 4.2 500 Unit V V us LPD enable LPD enable LPD enable and VDD20
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SH69P25
AC Characteristics Symbol TCY TIW TIWH TIWL Parameter Instruction Cycle Time T0 Input Width High Pulse Width LOW Pulse Width Min. 1 (TCY + 40)/N 1/2 tIW 1/2 tIW Typ. Max. 122 Unit s ns ns ns N = Prescaler divide ratio Condition
Timing Waveform
T0 Input Waveform
TiwH TiwL
T0 Tiw
Built-in RC Oscillator (Only use for Watch Dog)
RESET
OSC
WDT Built-in RC Tosc1 Twdt
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Typical RC oscillator Resistor vs. Frequency: (VDD = 5V, for reference only)
5V RC Frequency
10000.00
Fosc(kHz)
1000.00
100.00
10.00
60.00
110.00 160.00 210.00 260.00 310.00 360.00 R(k om)
Typical RC Oscillator Resistor vs. Frequency: (VDD = 3V, for reference only)
3V RC Frequancy
10000.00
Fosc(k Hz)
1000.00
100.00 10.00 60.00 110.00 160.00 210.00 260.00 310.00 360.00
R(k om)
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Application Circuit (for reference only)
AP1 (1) Operating voltage: 5.0V (2) Oscillator: Ceramic resonator 400kHz (3) T0 input timer clock / counter (4) PORTA - F: I/O
T0 VDD 47K
OSCI
SH69P25
RESET
OSCO PORTA ~ PORTF
20P
C1 0.1u GND
I/O
AP2 (1) Operating voltage: 5.0V. (2) Oscillator: RC 400KHz. (3) PORTA - E: I/O
VDD 47K 22K T0 OSCI
SH69P25
OSCO PORTA ~ PORTF
1000PF
C1 0.1u
I/O
GND
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AP3 (1) PORTA - C: as scan KEY BOARD (32 keys) (2) PORTD - F: I/O, (3) All input pin internal Pull up On
I/O
PORTD ~ PORTF
PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PA0 PA1 PA2 PA3
SH69P25
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Ap4 (Weight Scale) (1) Operating voltage: 5.0V (2) Oscillator: Ceramic resonator 4MHz (3) Port A0: External interrupt input for ON/OFF switch (4) Port E2, E3, F1, A2: S4 - S1 analog switch control signals that control Vil is being charged or discharged by both the reference voltage (Vref) and the amplified voltage (Vo). The charging and discharging times are determined by the values of C1, R4 and the threshold voltage of the T0 input pin and the ADC resolution can be up to 8 bit (5) Other Ports: Sink seven-segment LED current directly. 0 - 199 can be displayed in this configuration
VDD
Load Cell R2 R3 Vi R1 R2 R3
Vref R5
S1 S2 ON/OFF
Vo R4
S3
Vi1 1 S1 PE2 2 S2 PE3 3 S3 PF1 4 S4 PA2 5 6 PA3 7 T0 8 RESET GND 9 PB0 10 PB1 11 PB2 12 PB3 13 PD0 14 PD1 PE1 PE0 PF0 PA1 PA0 OSCI OSCO VDD PC3 PC2 PC1 PC0 28 27 26 25 24 23 22 21 VDD 20 19 18 17 16 PD3 15 PD2
C1 Instrumentation Amplifier R6
S4 100
C 1 4MHz 2 120P - 470P XC1 C 120P - 470P
Vo = (1 + 2R2/R1) (R4/R3)Vi
47K
0.1u
abc de f g
abc de f g
abc de f g
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Bonding Diagram
R E S E T
T 0
P A 3
P A 2
P F 1
P E 3
P E 2
P E 1
P E 0
P F 0
P A 1
P A 0
O S C I
7
6
5
4
3
2
1
28 27 26 25 24
23
GND1
8
SH69P25
Y (0,0) X
1879.6um
22
OSCO GND2
9
P B 0
10 11 12 13 14 15 16 17 18 19 20
P B 1 P B 2 P B 3 P D 0 P D 1 P D 2 P D 3 P C 0 P C 1 P C 2 P C 3
21
V
D D
1920.24um
NOTE: 1. GND1 BONDING TO GROUND PIN 2. GND2 BONDING TO SUBSTRATE 3. SUBSTRATE BONDING TO GROUND PIN
Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Designation PE 2 PE 3 PF 1 PA 2 PA 3 T0
RESET
unit: m
X -23 -153 -283 -413 -543 -673 -803 -818 -796 -666 -536 -406 -276 -146 -16 Y 749.5 749.5 749.5 749.5 749.5 749.5 749.5 585 -749.5 -749.5 -749.5 -749.5 -749.5 -749.5 -749.5 22 23 24 25 26 27 28 Pad No. 16 17 18 19 20 21 Designation PD 3 PC 0 PC 1 PC 2 PC 3 VDD GND2 OSCO OSCI PA 0 PA 1 PF 0 PE 0 PE 1 X 114 244 374 504 634 769 822 725 767 587 467 347 227 107 Y -749.5 -749.5 -749.5 -749.5 -749.5 -749.5 -619.5 -420 749.5 749.5 749.5 749.5 749.5 749.5
GND1 PB 0 PB 1 PB 2 PB 3 PD 0 PD 1 PD 2
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Ordering Information
Part No. SH69P25H SH69P25K SH69P25M Packages CHIP FORM 28L SKINNY 28L SOP
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Package Information
SKINNY_28L Outline Dimensions unit: inches/mm
D 28 15
E1
1 S
14 E C
A2
A1
A
Base Plane
L
Mounting Plane B e1 \ B1 eA
Symbol A A1 A2 B B1 C D E E1 e1 L \ eA S
Dimensions in inches 0.175 Max. 0.010 Min. 0.130 0.005 0.018 +0.004 -0.002 0.060 +0.004 -0.002 0.010 +0.004 -0.002 1.388 Typ. (1.400 Max.) 0.310 0.010 0.288 0.005 0.100 0.010 0.130 0.010 0 ~ 15 0.350 0.020 0.055 Max.
Dimensions in mm 4.45 Max. 0.25 Min. 3.30 0.13 0.46 +0.10 -0.05 1.52 +0.10 -0.05 0.25 +0.10 -0.05 35.26 Typ. (35.56 Max.) 7.87 0.25 7.32 0.13 2.54 0.25 3.30 0.25 0 ~ 15 8.89 0.51 1.40 Max.
Notes: 4. The maximum value of dimension D includes the end flash. 2. Dimension E1 does not include the resin fins. 5. Dimension S includes the end flash.
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SOP (N.B.) 28L Outline Dimensions
28 15 e1 ~ ~
unit: inches/mm
HE
E
L 1 D b 14
Detail F
e1 c A2 A
s Seating Plane
e
y D
A1
LE See Detail F
Symbol A A1 A2 b c D E e e1 HE L LE S y
Dimensions in inches 0.110 Max. 0.004 Min. 0.093 0.005 0.016 +0.004 -0.002 0.010 +0.004 -0.002 0.705 0.020 0.295 0.010 0.050 0.006 0.376 NOM. 0.406 0.012 0.036 0.008 0.055 0.008 0.043 Max. 0.004 Max. 0 ~ 10
Dimensions in mm 2.79 Max. 0.10 Min. 2.36 0.13 0.41 +0.10 -0.05 0.25 +0.10 -0.05 17.91 0.51 7.49 0.25 1.27 0.15 9.40 NOM. 10.31 0.31 0.91 0.20 1.40 0.20 1.09 Max. 0.10 Max. 0 ~ 10
1. 2. 3. 4.
Notes: The maximum value of dimension D includes end flash. Dimension E does not include resin fins. Dimension e1 is for PC Board surface mount pad pitch design reference only. Dimension S includes end flash.
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Product Spec. Change Notice SH69P25 Specification Revision History
Version Content Change "Max current into VDD pin" from 50mA to 100mA Change "Max. output current sunk by any I/O port " from25mA to 50mA Change "Max. Output current sourced by any I/O port" from 20mA to 40mA Delete the defination of "Max. Output current sunk by all ports (A, B, C, D, E, F) = 50mA", and "Max. Output current sourced by all ports (A, B, C, D, E, F) = 40mA" Add "In System Programming Notice for OTP" Reduce operating current. Add RC Frequency-Resistance diagram. Add bonding diagram Change LPD low level voltage range from 2.50.1 to 2.50.2 Original Date
1.01
Nov. 2003
1.0 0.1
May.2003 Sep.2002
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